The present invention relates to a testing apparatus for bumps at wafer level and a testing method thereof. Particularly, the present invention relates to an apparatus for testing conductive bumps formed on semiconductor components and the testing method thereof.
A flip chip microelectronic assembly includes direct electrical connection of face down, or “flipped”, electronic components to substrates, such as ceramic substrates, circuit boards, or carriers using conductive bump bonding pads. Flip chip technology is quickly replacing older wire bonding technology that uses face up chips with wire connected to each pad on the chip.
Flip chips are typically made by a process including placing solder bumps on a silicon wafer. The solder bump flip chip processing typically includes four sequential steps of preparing the wafer for solder bumping, forming or placing the solder bumps on the wafer, attaching the solder bumped die to a board, substrate or carrier, and completing the assembly with an adhesive underfill.
The bumps of the flip chip assembly also serve several functions. The bumps provide an electrical conductive path from the chip (or die) to the substrate on which the chip is mounted. A thermally conductive path is also provided by the bumps to carry heat form the chip to the substrate. The bumps also facilitate mechanical mounting of the chip to the substrate.
A few widely used methods of depositing bumps are evaporation, electroplating, electroless plating, sputtering and stencil-printing. The quality of the bumps formed on the semiconductor component, however, is a factor affecting reliability of the semiconductor chip after the flip-chip assembly. Poor bump formation may prevent the semiconductor chip from passing tests, especially the reliability tests.
Currently, however bumps formed on a semiconductor component by one of the described methods can only be tested after the flip-chip assembly of the semiconductor component is completed.
FIGS. 1 and 2 illustrate a conventional “daisy-chain” method testing method, for determining quality of conductive bumps. In FIG. 1, the daisy-chain method is achieved by first forming a bump array having a plurality of bumps 12 over a test die 10 of a semiconductor substrate (not shown) by any of the previously described bump forming methods. Every two bumps 12 are electrically connected by a segment 14 formed on the surface of the test die 10 to form a bump section 16. Each segment 14 is electrically conductive and a plurality of bump sections 16 can thus be formed over the test die 10 and each thereof is electrically separated. Further, second segment 18 can be formed over the test die 10 to properly connect two bump segments 16 for the purpose of line routing. The segment 14 and the second segment 18 can be a short metal segment or a bonding pad formed on the surface of the test die 10, the material thereof can be an electrically conductive material such as aluminum or aluminum alloy.
As shown in FIG. 2, the test die 10 having a plurality of bump sections 16 in FIG. 1 is then assembled on a test board 20 having a plurality of third segments 22 and solder balls 24 formed thereon. The third segment 22 and the solder balls 24 are also electrically conductive. Each bump section 16 on the test die 10 is disposed over a position complementary to an pair of adjacent third segments 22 thereof and thus a single electrically conductive path (not shown) can be formed after the assembly of the test die 10. The test board 20 and a test such as an impedance test for the bumps 12 can then be performed by a testing apparatus such as a burn-in socket to examine not only the quality of bumps but also the conditions of the bumping process. The conventional daisy-chain method, however, labor intensive and time consuming. Further, the daisy-chain method cannot be applied to the testing of product dies in modern IC industries and is used only when evaluating a bumping process and process parameters thereof.
Hence, there is a need for an apparatus for instantaneously testing conductive bumps. In U.S. patent application publication US2003/0141883, Mitchell et. al. provide a probe card testing apparatus which includes a pair of side by side and parallel probes for contacting a single conductive ball or contact point for the purpose and benefit of correcting contaminant layer IR voltage drops using Kelvin techniques.